The main application of the invention resides in the field of microelectronics, for the metallization, particularly with copper, of vias (called “through-silicon vias” (TSV) or “through-wafer vias” or “through-wafer interconnects”), the keystone for the three-dimensional (3D) integration, or vertical integration, of electronic chips (or dies). Such vias have typical hole size ranging between 0.5 μm and 500 μm, most commonly between 5 μm and 100 μm; and typical depth ranging between 10 μm and 750 m, most commonly between 50 μm and 300 μm. It also has applications in other fields of electronics where a substrate comprising vias must be electrically insulated and covered with a layer of copper. In this context can be mentioned the formation of interconnecting elements between printed circuit boards (or printed wire boards), of passive elements such as inductors, or of electromagnetic elements in integrated circuits or micro-electromechanical systems, or of metallization schemes for photovoltaic cells
Current electronic systems mostly consist of several integrated circuits, or components, and each integrated circuit fulfils one or more functions. For example, a computer comprises at least one microprocessor and several memory circuits. Each integrated circuit usually corresponds to an electronic chip in its own package. The integrated circuits are soldered to or plugged into, for example, a printed circuit board (PCB) which ensures the connection between the integrated circuits.
The permanent need to increase the functional density of electronic systems has led, according to a first approach, to the so-called “system-on-chip” concept, with all the components and circuit units necessary to implement all the system functions being produced on the same chip without using a printed circuit support. In practice it is nonetheless very difficult to obtain a high-performance system-on-chip as the manufacturing methods for logic and memory circuits, for example, differ very substantially from each other. The system-on-chip approach therefore requires the acceptance of compromises with respect to the performance of various functions produced on the same chip. In addition, the size of such chips and their manufacturing efficiency are reaching the limits of their economic feasibility.
A second approach consists in forming in one and same package a module ensuring the interconnection of several integrated circuits, which may be formed on the same semiconductor substrate or on different substrates. The package thus obtained, or the multichip module (MOM) or System-in-Package (SiP) or System-On-a-Package (SOP), thus takes the form of a single component. This MOM approach makes it possible to obtain a higher interconnection density and therefore better performance than a conventional PCB approach. It is however not fundamentally distinguished from the PCB approach. Apart from the bulk and the weight of the package, the performance of an MOM remains limited by the electromagnetic interferences associated with the length of the connections from the substrate and with the wire bonds connecting the substrate or the chips to the pins of the package.
A third approach, called three-dimensional (3D) integration or vertical integration, is characterized by the fact that the chips are stacked and connected to each other by vertical interconnections drilled through the chip's material, electrically connecting the top surface with the bottom surface of the chip. The stack obtained thus comprises several layers or strata of active components or chips, and constitutes a 3D integrated circuit (or 3D IC).
The benefits of 3D integration are based on:
(1) improvement in performance, e.g. reduction in propagation time and in dissipated power, increase in the operating speed of the system associated with the accelerated communication between the functional units, increase in the bandwidth of each functional unit, increase in noise immunity;
(2) improved cost-effectiveness, e.g. increase in integration density, improved manufacturing efficiency due to the use of the electronic chip technology which is most appropriate for each functional unit, improved reliability; and
(3) the possibility of producing highly integrated systems by stacking heterogeneous technologies (or co-integration), i.e. employing different materials and/or different functional components.
As a result, 3D integration today constitutes an essential alternative to the conventional approaches, which are reaching their limits in terms of performance, functional diversification and production costs. The foundations and advantages of 3D integration have been described, for example, in: A. W. Topol et al., “Three-dimensional integrated circuits” IBM Journal Res. & Dev., no. 4/5 July/September 2006, 50, 491-506.
After stacking, for example by bonding, the chips may be individually connected to the pins of the package by wire bonding or flip-chip connections. The interconnections between the chips are generally carried out by employing TSVs.
The elementary technologies necessary for the production of 3D integrated circuits comprise in particular thinning the silicon wafers, aligning the layers, bonding the layers, and etching and metallizing the TSVs within each layer.
The thinning of silicon wafers may be carried out before forming the TSVs (e.g. U.S. Pat. No. 7,060,624, U.S. Pat. No. 7,148,565).
Alternatively, the etching and the metallization of vias may be carried out before thinning the silicon wafer (e.g. U.S. Pat. No. 7,060,624, U.S. Pat. No. 7,101,792). In this case, closed vias or blind vias are etched in the silicon on one side of the wafer to the desired depth, then metallised throughout before thinning the silicon wafer from the other side in order to expose the buried end of the metallization and thus obtain through-silicon vias.
The good electrical conductivity of copper and its high resistance to electro-migration, i.e. the low tendency of copper atoms to migrate under the effect of the electrical current density, which can be an important cause of failure, make it in particular a material of choice for the metallization of vias.
The vias of 3D integrated circuits are generally made in a manner similar to the “Damascene method” used in the field of microelectronics for forming elements for interconnecting integrated circuits, according to a series of steps comprising:
the etching of vias in or through the silicon wafer and through the Back-End-Of-Line (BEOL) stack if necessary (e.g. for via-last structures);
the deposition of an insulating dielectric layer, or liner;
the deposition of a barrier layer, serving to prevent the migration or diffusion of copper;
the optional deposition of a seed layer to improve the electro-deposition of copper in case the selected barrier material has a very low electrical conductivity
the filling of the vias by electro-deposition of copper; and
the elimination of excess copper and barrier from the wafer surface by chemical-mechanical polishing.
As mentioned above, the invention is more particularly directed to the fabrication of “via-last structures”, i.e. TSVs formed in the integrated circuit, following the BEOL steps, by opposition with “via first” (which are formed prior to the front-end-of-line (FEOL) steps) and “via middle” (which are formed following FEOL steps but prior to the BEOL steps).
The “via first” method involves forming the TSVs in a substrate before any other fabrication of circuitry occurs. A pattern of vias is etched or drilled into a fraction of the depth of the base substrate. The vias are then filled with an insulating layer and conducting material and circuit manufacturing follows. One or more dies can then bond to the TSVs. The back side of the substrate containing the TSVs is ground down to expose the TSVs. Metallization of the exposed TSVs enables packaging of the multi-tiered structure.
In the “via last” method, circuit manufacturing and optional wafer thinning take place before the TSVs are formed. The circuitry contains interconnect conductive pads that will be coupling points for the TSVs. TSVs are created by either etching or drilling to the conductive pad through the depth of the substrate or etching or drilling from the back side of the substrate to the conductive pad. The TSV is then filled with an insulating layer and conducting material. The back of the substrate is metalized to enable packaging of the multi-tiered structure.
The distinction between the different kinds of TSVs being well-known by the skilled person, it will not be further discussed here. Nevertheless, one can refer to “Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits”, Ph. Garrou et al., WILEY-VCH, 2009 in order to have additional information.
Usually, via-last TSVs are formed in accordance with the following steps:
providing a layered semiconductor structure, said layered semiconductor structure comprising:
a support substrate including a first surface and a back surface,
at least one insulating layer overlying the first surface of the support substrate; most commonly a stack of insulating layers from different materials is used; and
at least one conductive pad formed within the insulating layer; and
drilling a via from the back surface of the support substrate.
The drilling is usually formed by dry etching, in order to obtain straight walls for the via and thus facilitate the uniform coating of the via with the insulating layer.
However, different materials must be etched (typically a first insulation layer, the wafer silicon bulk, and the layered semiconductor structure described above), so different methods and tools must be used in a predetermined sequence. The limitation of this method is linked to the difficulty of stopping the process at the right moment, i.e. to completely remove the required material without damaging the metal pad and to avoid the resputtering of its conductive material (usually, copper), i.e. ejection of conductive material towards the walls of the via, which can later induce short-circuits at the active device's junctions due to the diffusion of unwanted copper ions into the silicon bulk.
As a consequence, in spite of the aforementioned drawbacks, dry etching is still privileged over other known techniques since it is a simple and common way to rapidly obtain a straight via in an integrated circuit.
An insulating film is then coated on the via walls by conventional techniques such as deposition. These methods however also coat the conductive pad and the existing insulating layer(s), so that an additional step to remove the insulating film at least from the conductive pad becomes necessary, in order to enable connection with the components.
There is therefore a need for a method that overcomes the aforementioned drawbacks.